EN0-001 ARM Accredited Engineer Free Practice Exam Questions (2025 Updated)
Prepare effectively for your ARM EN0-001 ARM Accredited Engineer certification with our extensive collection of free, high-quality practice questions. Each question is designed to mirror the actual exam format and objectives, complete with comprehensive answers and detailed explanations. Our materials are regularly updated for 2025, ensuring you have the most current resources to build confidence and succeed on your first attempt.
A software profiling tool records the address held in the Program Counter (PC) every 1 ms. The software function that resides at each recorded address can be determined by the profiling tool. The percentage of time spent in each function is calculated from the percentage of recorded addresses where each function is resident.
Which one of the following statements is FALSE?
In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)
In an MPCore system, when one core is waiting for resources to be released, what instruction could be used to reduce that core's power consumption?
Which of these instructions is a correct translation of the body of function f?
struct T { char a; int b; };
int f(struct T *p) { return p->b; }
What are the values of the NZCV bits in the CPSR after executing the following instructions?
LDR R0, = 0xFFFFFFFF
ADDS R0, R0, #1
An external debugger would need to clean the contents of the processor data cache in which of the following cases?
Assume a multicore processor with coherency management based on the MESI protocol. When a core changes the contents of a shared cache line, what is the final status of that line in the local cache?
The Cortex-A9 MPCore processor contains a hardware block whose function is to maintain data cache coherency between cores. What is the name of this block?
In a Cortex-A9 processor, CP14 system control registers are used for:
The Cortex-A9 processor has 6 breakpoint units and 4 watchpoint units. What is the maximum number of breakpoints the debugger can set on code in ROM?
The disassembly of a program written in C shows calls to the function__aeabi_fadd. Which one of these compiler floating point options could have been used?
Which of the following best describes the relationship between Tightly Coupled Memories (TCM), Level 1 (L1) and Level 2 (L2) cache memory systems?
How many ARM core registers and PSRs (Program Status Registers) are available to the programmer in User mode on a Cortex-A9?
The Cortex-A9 processor implements a feature called "small loop mode" which reduces power consumption when executing small loops by turning off instruction cache accesses. Which of the following statements describes a condition that must be satisfied for this mode to be enabled?
Which of these processors is only available as a single core configuration?
Which of the following processors includes a Generic Interrupt Controller as a standard component?
Consider the following instruction sequence:
STR r0, [r2] ; instruction A
DSB
ADD r0, r1, r2 ; instruction B
LDR r3, [r4] ; instruction C
SUB r5, r6, #3 ; instruction D
At what point will execution pause until the STR access is complete?
Within the ARMv7 architecture, which one of the following features is unique to the ARMv7-A profile?
When programming in C, how many bytes of stack are needed to pass parameters when calling the following function?
int foo( int arg_a, int arg_b, int arg_c )
Which of the following features was added in version 2 of the ARM Architecture Advanced SIMD extensions?
